| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-06-05 | [aarch64] Emit abs, min, and max instructions during lifting | Mark Rowe | |
| 2026-06-05 | [aarch64] Fix incorrect lifting of double precision FMOV immediate | Mark Rowe | |
| 2026-06-04 | [aarch64] Emit bswap, popcnt, clz, ctz, cls, and rbit instructions during ↵ | Mark Rowe | |
| lifting Intrinsics are still used when lfiting vector instructions, and for 64-bit `rev16` instructions that are not easily composed from the new instructions. | |||
| 2026-05-22 | Add handling of structure returns and parameters in aarch64 calling convention | Rusty Wagner | |
| 2026-04-22 | [arm64] Update header names in Makefiles | fG! | |
| The names of generated headers were not updated after they were changed in b095215397ca. | |||
| 2026-04-14 | [aarch64] Fix handling of ARM64_RELOC_GOT_LOAD_PAGEOFF12 and ↵ | Josh Ferrell | |
| ARM64_RELOC_GOT_LOAD_PAGE21 | |||
| 2026-04-13 | [aarch64] Add support for ARM64_RELOC_BRANCH26, ARM64_RELOC_GOT_LOAD_PAGE21, ↵ | Josh Ferrell | |
| ARM64_RELOC_GOT_LOAD_PAGEOFF12 | |||
| 2026-03-23 | [Swift] Add arm64 calling conventions | Mark Rowe | |
| The Swift ABI repurposes three callee-saved registers for implicit parameters (self, error, and async context). Supporting the various combinations of these requires registering several different calling conventions. The demangler is taught to explicitly apply these calling conventions to functions that need them. | |||
| 2026-02-27 | [MachO] Fix relocations from chained fixups not respecting addends | Mark Rowe | |
| The addends were correctly stored in the relocation info and displayed as offsets in linear view, but the relocation handlers never applied them. Reading from an address containing such a relocation would give an incorrect value. | |||
| 2026-02-09 | Fix outdated object names in AArch64 disassembler Makefiles | Jon Palmisciano | |
| 2026-01-30 | Update function recognizer to detect ILP32 plt entries | Brandon Miller | |
| 2026-01-01 | update copyrights for 2026 | Jordan Wiens | |
| 2025-12-29 | Use session scoped logger instance for unhandled relocation information | Mason Reed | |
| Ran into this when running over certain object files on ppc, we can do it for all of them though. | |||
| 2025-12-20 | Fix many of the warnings that show up when compiling with GCC 15.2 | Mark Rowe | |
| 2025-12-08 | [AArch64] Update system registers based on ARM's 2025-09 data | Mark Rowe | |
| This change consists of two parts: 1. Updating the system register enumeration and names based on the latest data from ARM. 2. Removing register names that conflict with the official names from ARM. The conflicting register names came a data set of Apple-specific system register names. These would ideally not be baked into the AArch64 disassembler at all, but would be added by Binary Ninja's Apple platform. The exact mechanism for doing that is still TBD. Fixes https://github.com/Vector35/binaryninja-api/issues/7664. | |||
| 2025-11-05 | [ARM64] only extend if load is small | yrp | |
| [ARM64] remove zero extend from ubfx, ubfiz [ARM64] only zero extend fmov when needed arm64: resolve ambiguity Resolves #7307 | |||
| 2025-10-24 | aarch64: implements lifting (intrinsics) for LDXP/STXP | Maxime Meignan | |
| 2025-10-20 | [AArch64] Lift MTE instructions to intrinsics | Mark Rowe | |
| 2025-10-18 | [AArch64] Lift FEAT_CSSC instructions | Mark Rowe | |
| `abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction sequences involving comparisons, while `cnt` and `ctz` are lifted to intrinsics. | |||
| 2025-10-15 | [AArch64] Update disassembler based on 2025-09 ARM ISA data | Mark Rowe | |
| 2025-09-25 | [AArch64] Update disassembler based on 2025-06 ARM ISA data | Mark Rowe | |
| Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. | |||
| 2025-09-18 | fix ldrsw lift to sign extend in certain encodings | yrp | |
| 2025-09-11 | Add Apple arm64 syscall calling convention to Apple's platforms | mostobriv | |
| 2025-09-08 | [aarch64] Enable Always and Never Branch patching for TBZ/TBNZ and CBZ/CBNZ | Galen Williamson | |
| 2025-08-05 | [ARM64] Fix lifting of mrs xzr, ... to not reference the xzr register | Mark Rowe | |
| ARM64 lifting replaces references to the zero register with constant zeroes. The zero register is not intended to appear in any lifted IL. In the case of the `mrs` instruction, the destination being a zero register means the system register is accessed only for a side-effect, and is not stored anywhere. The lifting is updated to specify no output registers for the intrinsic in that case. | |||
| 2025-07-30 | [CMake] Specify CONFIGURE_DEPENDS for all file(GLOB ..) | Mark Rowe | |
| This ensures that CMake detects when files that match the glob are added or removed. | |||
| 2025-07-30 | [ARM64] Fix lifting of tbz / tbnz for bits >= 32 | Mark Rowe | |
| 2025-06-25 | Update CXX_STANDARD to 20. | Alexander Taylor | |
| Also update minimum CMake version. | |||
| 2025-06-25 | Remove implicit conversions from Confidence to underlying type, these can ↵ | Rusty Wagner | |
| cause bugs and also issues with C++20 | |||
| 2025-06-02 | ARM64 disassembler: fix MSVC compilation | justanotheranonymoususer | |
| 2025-05-28 | PR #6757: prefer fp, lr for x29, x30 | yrp | |
| arm64: prefer fp, lr arm64: update tests to use new reg names, improve windows build | |||
| 2025-05-28 | Revert "Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c" | Galen Williamson | |
| This reverts commit cb7c2d3bb716a2e96cf7f127bbf71992a4861907. | |||
| 2025-05-27 | Update decode_scratchpad.c | justanotheranonymoususer | |
| 2025-05-27 | Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c | justanotheranonymoususer | |
| MSVC shows several warnings, but this one is shown as an error, preventing compilation. | |||
| 2025-05-13 | [CMake] Report compatibility with 3.15 to silence deprecation warnings | Glenn Smith | |
| 2025-04-09 | [aarch64] add lifting for B.NV instruction, fix branch generation for B.AL ↵ | Galen Williamson | |
| and B.NV, fix AlwaysBranch patching to generate a valid B instruction | |||
| 2025-04-09 | [aarch64] add lifting for B.AL instruction | Galen Williamson | |
| 2025-04-09 | Fix capitalization of AArch64. | Alexander Taylor | |
| 2025-04-08 | [aarch64] remove "unknown hint" warning | Galen Williamson | |
| 2025-04-08 | [aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵ | Galen Williamson | |
| ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi | |||
| 2025-04-01 | [aarch64] use static var to avoid recreation of sysregs vector | Galen Williamson | |
| 2025-03-31 | [aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵ | Galen Williamson | |
| lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands | |||
| 2025-03-28 | belated copyright year update | Jordan Wiens | |
| 2025-03-19 | Register relocation handlers for KCView type | kat | |
| 2025-02-12 | bugfix: ARM64: missing break in il.cpp's switch | Maxime Meignan | |
| A `break` was missing in the switch, making the LDXRH instruction generate 2 IL instructions | |||
| 2025-01-15 | [aarch64] fix size of immediate arguments in intrinsic calls | Galen Williamson | |
| 2024-10-23 | Calling Conventions for register specific arc functions | kat | |
| 2024-09-14 | Add mpidr_el1 aarch64 sysreg | Josh Ferrell | |
| 2024-09-13 | Fix many warnings | Josh Ferrell | |
| 2024-09-13 | Ultimate. | Alexander Taylor | |
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