| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-05-13 | [CMake] Report compatibility with 3.15 to silence deprecation warnings | Glenn Smith | |
| 2025-04-28 | [thumb2] correctly set flags for mov{s} and mvn{s} instruction variants with ↵ | Galen Williamson | |
| 32-bit encodings, addresses #6698 | |||
| 2025-04-08 | [aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵ | Galen Williamson | |
| ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi | |||
| 2025-03-28 | belated copyright year update | Jordan Wiens | |
| 2025-03-06 | ARMv7: Fix lifting of instructions that use register-shifted registers | Josh Ferrell | |
| 2025-03-06 | ARMv7: update test_lift.py and test.py | Josh Ferrell | |
| 2025-03-06 | ARMv7: Add support for register-shifted registers | Josh Ferrell | |
| 2025-02-05 | Fixes: Unsupported ELF relocations: R_ARM_THM_MOVW_ABS_NC, ↵ | Galen Williamson | |
| R_ARM_THM_MOVT_ABS #6215 | |||
| 2025-02-02 | Fix upper 16 registers not being listed in ARMv7 register list operand | Mason Reed | |
| Fixes #6383 | |||
| 2025-01-17 | [thumb2] Fix #6328: "Invalid intrinsic lifting for MRS instruction: ↵ | Galen Williamson | |
| destination register incorrectly specified" by correctly specifying the intrinsic outputs | |||
| 2024-09-13 | Ultimate. | Alexander Taylor | |
| 2024-08-27 | Fixed fall-through VMOV lifting | Galen Williamson | |
| Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV | |||
| 2024-08-27 | Cleaned up formatting on new and old code | Galen Williamson | |
| 2024-08-27 | Constraint NEON instructions using operation flags | Mason Reed | |
| Also fix some formatting issues | |||
| 2024-08-27 | Use split registers for VMOV | Mason Reed | |
| 2024-08-27 | Fix VPOP not setting registers | Mason Reed | |
| 2024-08-27 | Fix VDIV constraints and lift VNEG | Mason Reed | |
| 2024-08-27 | Fix unconstrained VADD and VABS | Mason Reed | |
| 2024-08-27 | Lift VMRS and mark system registers | Mason Reed | |
| System registers needed to be marked to prevent the registers from being passed as arguments | |||
| 2024-08-27 | Lift VSUB, VDIV, VMUL, VFMA | Mason Reed | |
| VSUB already existed but it was lifted as a regular SUB instruction | |||
| 2024-08-27 | Lift more variants of VCVT and correct a missed variant case | Mason Reed | |
| 2024-08-27 | Lift VSTMIA, VLDMIA | Mason Reed | |
| 2024-08-27 | Fix non R register groups referencing PC for 15th register index | Mason Reed | |
| Any usage of d15, s15, q15 was completely broken | |||
| 2024-08-27 | Lift misc V_ thumb instrunctions | Mason Reed | |
| 2024-08-27 | Lift VMOV | Mason Reed | |
| 2024-08-27 | Lift VLDR and VSTR | Mason Reed | |
| 2024-08-27 | Lift VPOP and VPUSH | Mason Reed | |
| 2024-08-27 | Fix getting incorrect S and D registers in lifted il | Mason Reed | |
| 2024-08-27 | Remove duplicate conditional checks in v_ lifts | Mason Reed | |
| 2024-08-21 | Fix thumb2 lifting of REV | Mason Reed | |
| 2024-08-06 | Add flag role for carry flag when subtraction is implemented with addition | Rusty Wagner | |
| 2024-07-24 | change parameter name to align the function definition | Zichuan Li | |
| A user reported in public slack that the definition doesn't agree on endianness | |||
| 2024-03-15 | Separate local variable tokens in higher level ILs from stack variable ↵ | Rusty Wagner | |
| tokens in lower levels, and improve token usage in disassembly | |||
| 2024-03-12 | moved over from https://github.com/Vector35/arch-armv7/pull/81 | Galen Williamson | |
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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