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2026-01-23Lifted new PPC insns, MIPS reloc fix.Alexander Taylor
2026-01-20swap order for some ppc floating point that were backwardJordan Wiens
2025-11-03Fix VLE ANDIx translation to always store result in destination registerchedahub
2025-10-29Fix(ppc/il): Treat r0 as a register in e_addi/e_add16i ILchedahub
2025-06-29[powerpc] Full merge of PowerPC disassembler PRs, including:Galen Williamson
* Remove dependency on capstone for PowerPC disassembly #6292 * Add support for PowerPC VLE instruction set #6740 * Add support for paired-single instructions #6821 * Various post-merge fixes and tweaks to disassembly and lifting * Removal of dependence on capstone for assembler's scoring mechanism (capstone currently disabled, but not removed from codebase yet)
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵Galen Williamson
ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
2025-02-06[mips] Fix decoding of MIPS ds*32 instructions, add lifting for MIPS drotr* ↵Galen Williamson
instructions; clean up some warnings in powerpc/il.cpp
2024-12-16[ppc] merges PR Vector35/binaryninja-api#5176 (adds support for "psq" ↵Galen Williamson
Quantized Floating Point instructions, fixes/completes 64-bit instruction/register support)
2024-11-06Fixes Vector35/binaryninja-api#5968: "PowerPC flag names no longer ↵Galen Williamson
recognized (due to changes in capstone register numbering)": handles new capstone flag numbers, allows assembling `isel` instructions with capstone syntax, disassembles flag registers with capstone syntax
2024-03-26added lifting for EXTSW LD LDU LDUX LDX SLD SRAD SRADI SRD STD STDU STDUX STDXGalen Williamson
2024-03-05Move architecture modules into the API repoRusty Wagner