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2025-05-28Revert "Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c"Galen Williamson
2025-05-27Update decode_scratchpad.cjustanotheranonymoususer
2025-05-27Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.cjustanotheranonymoususer
2025-05-13[yasm] Fix warning for use of deprecated FindPythonGlenn Smith
2025-05-13[CMake] Report compatibility with 3.15 to silence deprecation warningsGlenn Smith
2025-05-12[Rust] Remove `NonSSAVariant` bound from `LowLevelILFunction`Mason Reed
2025-05-12[Rust] Remove unneeded mut from Architecture trait signaturesMason Reed
2025-05-12[Rust] Support SSA form properly in low level ILMason Reed
2025-05-12[Rust] Remove Architecture trait bound on LLIL related structuresMason Reed
2025-05-12[Rust] Pretty print LLIL sub expressionsMason Reed
2025-04-28[thumb2] correctly set flags for mov{s} and mvn{s} instruction variants with ...Galen Williamson
2025-04-24mips: fix mips32 linux-syscall cc stack behaviorRyan Snyder
2025-04-14[powerpc] Fix incorrect disassembly of LIS, ADDIS, ANDI, ANDIS; add assembly ...Galen Williamson
2025-04-09[aarch64] add lifting for B.NV instruction, fix branch generation for B.AL an...Galen Williamson
2025-04-09[aarch64] add lifting for B.AL instructionGalen Williamson
2025-04-09[mips] always show 0 offset in MIPS operands using Register + Offset Addressi...Galen Williamson
2025-04-09Fix capitalization of AArch64.Alexander Taylor
2025-04-08[aarch64] remove "unknown hint" warningGalen Williamson
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ST...Galen Williamson
2025-04-08Omit the branch when lifting xabortBrandon Miller
2025-04-01[aarch64] use static var to avoid recreation of sysregs vectorGalen Williamson
2025-03-31[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lift...Galen Williamson
2025-03-28missed the older dates!Jordan Wiens
2025-03-28belated copyright year updateJordan Wiens
2025-03-24Fix extern ptr corercion for R_MIPS_HIGHEST/HIGHERBrandon Miller
2025-03-21fix x86 settings text and use proper raw string markerJordan Wiens
2025-03-19Register relocation handlers for KCView typekat
2025-03-06ARMv7: Fix lifting of instructions that use register-shifted registersJosh Ferrell
2025-03-06ARMv7: update test_lift.py and test.pyJosh Ferrell
2025-03-06ARMv7: Add support for register-shifted registersJosh Ferrell
2025-02-13Add licensing check for Rust codeMason Reed
2025-02-12bugfix: ARM64: missing break in il.cpp's switchMaxime Meignan
2025-02-10[mips] Merging PR https://github.com/Vector35/binaryninja-api/pull/6013: addi...Galen Williamson
2025-02-06[mips] Fix decoding of MIPS ds*32 instructions, add lifting for MIPS drotr* i...Galen Williamson
2025-02-05Fixes: Unsupported ELF relocations: R_ARM_THM_MOVW_ABS_NC, R_ARM_THM_MOVT_ABS...Galen Williamson
2025-02-02Fix upper 16 registers not being listed in ARMv7 register list operandMason Reed
2025-01-25Rust refactorMason Reed
2025-01-17[thumb2] Fix #6328: "Invalid intrinsic lifting for MRS instruction: destinati...Galen Williamson
2025-01-15[aarch64] fix size of immediate arguments in intrinsic callsGalen Williamson
2024-12-16[ppc] merges PR Vector35/binaryninja-api#5176 (adds support for "psq" Quantiz...Galen Williamson
2024-12-14Pass length to free flag conditions list callback and remove libc from rust apiMason Reed
2024-12-13Bump supported rust version to 1.83.0Mason Reed
2024-12-03Multiple fixes for HI16/LO16 relocs for MIPS64Brandon Miller
2024-11-30Run `cargo fmt` on RISC-V architectureMason Reed
2024-11-30Remove temp register in JALR RISC-V when unusedMason Reed
2024-11-30Update RISC-V function import recognizerMason Reed
2024-11-29Fix RISC-V JALR lift when rs1==rdMitchell Johnson
2024-11-25Fix shrx, shlx, sarx, rorxyrp
2024-11-25RISC-V: Implements MULH, MULHU, MULHSU liftingJean-Michel Deva
2024-11-25Fix regression with MIPS_HI16/MIPS_LO16 relocsBrandon Miller