diff options
| author | Mark Rowe <mark@vector35.com> | 2025-12-19 11:12:20 -0800 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-12-20 21:34:49 -0800 |
| commit | ed0f3b1b8593f6b76fbb64c53a0885073c1c1979 (patch) | |
| tree | 5d22d77ccea8bffc0619a32ed886d79d14daccf1 /arch/arm64/disassembler | |
| parent | ba13f6ec7d0ce9a18a03a1c895fb72d18e03014a (diff) | |
Fix many of the warnings that show up when compiling with GCC 15.2
Diffstat (limited to 'arch/arm64/disassembler')
| -rw-r--r-- | arch/arm64/disassembler/decode_scratchpad.c | 9 | ||||
| -rw-r--r-- | arch/arm64/disassembler/format.c | 3 | ||||
| -rw-r--r-- | arch/arm64/disassembler/pcode.c | 40 |
3 files changed, 23 insertions, 29 deletions
diff --git a/arch/arm64/disassembler/decode_scratchpad.c b/arch/arm64/disassembler/decode_scratchpad.c index f869889f..d1160980 100644 --- a/arch/arm64/disassembler/decode_scratchpad.c +++ b/arch/arm64/disassembler/decode_scratchpad.c @@ -1086,9 +1086,12 @@ static const char* const reg_lookup_c[16] = {"c0", "c1", "c2", "c3", "c4", "c5", i++; #define ADD_OPERAND_FLOAT32(VALUE) \ - instr->operands[i].operandClass = FIMM32; \ - *(float*)&(instr->operands[i].immediate) = VALUE; \ - i++; + do { \ + float value = VALUE; \ + instr->operands[i].operandClass = FIMM32; \ + memcpy(&instr->operands[i].immediate, &value, sizeof(float)); \ + i++; \ + } while (0) #define ADD_OPERAND_CONST ADD_OPERAND_IMM64(const_, 0) #define ADD_OPERAND_FBITS ADD_OPERAND_IMM32(fbits, 0) diff --git a/arch/arm64/disassembler/format.c b/arch/arm64/disassembler/format.c index 0db5ffbc..73f82a6f 100644 --- a/arch/arm64/disassembler/format.c +++ b/arch/arm64/disassembler/format.c @@ -383,7 +383,8 @@ uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, cha } if (type == FIMM32) { - float f = *(const float*)&instructionOperand->immediate; + float f = 0.0f; + memcpy(&f, &instructionOperand->immediate, sizeof(float)); if (snprintf(outBuffer, outBufferSize, "#%.08f%s", f, shiftBuff) >= outBufferSize) return FAILED_TO_DISASSEMBLE_OPERAND; } diff --git a/arch/arm64/disassembler/pcode.c b/arch/arm64/disassembler/pcode.c index 7993e312..46ffdcec 100644 --- a/arch/arm64/disassembler/pcode.c +++ b/arch/arm64/disassembler/pcode.c @@ -584,37 +584,29 @@ uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width) https://github.com/Siguza/iometa/blob/master/src/a64.c */ uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8) { - uint64_t imm64; switch ((cmode >> 1) & 0b111) { case 0b000: - imm64 = Replicate(imm8, 2, 32); - break; + return Replicate(imm8, 2, 32); case 0b001: - imm64 = Replicate(imm8 << 8, 2, 32); - break; + return Replicate(imm8 << 8, 2, 32); case 0b010: - imm64 = Replicate(imm8 << 16, 2, 32); - break; + return Replicate(imm8 << 16, 2, 32); case 0b011: - imm64 = Replicate(imm8 << 24, 2, 32); - break; + return Replicate(imm8 << 24, 2, 32); case 0b100: - imm64 = Replicate(imm8, 4, 16); - break; + return Replicate(imm8, 4, 16); case 0b101: - imm64 = Replicate(imm8 << 8, 4, 16); - break; + return Replicate(imm8 << 8, 4, 16); case 0b110: - imm64 = Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32); - break; + return Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32); case 0b111: switch (((cmode & 0b1) << 1) | op) { case 0b00: - imm64 = Replicate(imm8, 8, 8); - break; + return Replicate(imm8, 8, 8); case 0b01: + { #if 0 imm8a = Replicate((imm8 >> 7) & 0b1, 8, 1); imm8b = Replicate((imm8 >> 6) & 0b1, 8, 1); @@ -626,26 +618,24 @@ uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8) imm8h = Replicate((imm8 ) & 0b1, 8, 1); imm64 = (imm8a << 0x38) | (imm8b << 0x30) | (imm8c << 0x28) | (imm8d << 0x20) | (imm8e << 0x18) | (imm8f << 0x10) | (imm8g << 0x08) | imm8h; #else - imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) | + uint64_t imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) | (imm8 << (0x20 - 4)) | (imm8 << (0x28 - 5)) | (imm8 << (0x30 - 6)) | (imm8 << (0x38 - 7)); imm64 &= 0x0101010101010101; - imm64 = Replicate(imm64, 8, 1); + return Replicate(imm64, 8, 1); #endif - break; + } case 0b10: - imm64 = Replicate((((imm8 & 0xc0) ^ 0x80) << 24) | + return Replicate((((imm8 & 0xc0) ^ 0x80) << 24) | (Replicate((imm8 >> 6) & 0b1, 5, 1) << 25) | ((imm8 & 0x3f) << 19), 2, 32); - break; case 0b11: - imm64 = (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) | + return (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) | ((imm8 & 0x3f) << 48); - break; } break; } - return imm64; + return 0; } bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype) |
