| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-30 | Update function recognizer to detect ILP32 plt entries | Brandon Miller | |
| 2025-12-29 | Use session scoped logger instance for unhandled relocation information | Mason Reed | |
| Ran into this when running over certain object files on ppc, we can do it for all of them though. | |||
| 2025-10-24 | aarch64: implements lifting (intrinsics) for LDXP/STXP | Maxime Meignan | |
| 2025-10-20 | [AArch64] Lift MTE instructions to intrinsics | Mark Rowe | |
| 2025-10-18 | [AArch64] Lift FEAT_CSSC instructions | Mark Rowe | |
| `abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction sequences involving comparisons, while `cnt` and `ctz` are lifted to intrinsics. | |||
| 2025-09-11 | Add Apple arm64 syscall calling convention to Apple's platforms | mostobriv | |
| 2025-09-08 | [aarch64] Enable Always and Never Branch patching for TBZ/TBNZ and CBZ/CBNZ | Galen Williamson | |
| 2025-06-25 | Remove implicit conversions from Confidence to underlying type, these can ↵ | Rusty Wagner | |
| cause bugs and also issues with C++20 | |||
| 2025-04-09 | [aarch64] add lifting for B.NV instruction, fix branch generation for B.AL ↵ | Galen Williamson | |
| and B.NV, fix AlwaysBranch patching to generate a valid B instruction | |||
| 2025-04-09 | Fix capitalization of AArch64. | Alexander Taylor | |
| 2025-04-08 | [aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵ | Galen Williamson | |
| ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi | |||
| 2025-04-01 | [aarch64] use static var to avoid recreation of sysregs vector | Galen Williamson | |
| 2025-03-31 | [aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵ | Galen Williamson | |
| lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands | |||
| 2025-03-19 | Register relocation handlers for KCView type | kat | |
| 2024-10-23 | Calling Conventions for register specific arc functions | kat | |
| 2024-09-14 | Add mpidr_el1 aarch64 sysreg | Josh Ferrell | |
| 2024-09-13 | Ultimate. | Alexander Taylor | |
| 2024-09-08 | Respect ELF view endianness when calculating AArch64 relocations | Michael Krasnitski | |
| 2024-08-06 | Add flag role for carry flag when subtraction is implemented with addition | Rusty Wagner | |
| 2024-07-08 | [arm64] Full review of intrinsics; lifting of many instructions added, ↵ | Galen Williamson | |
| improved, and/or fixed Merged https://github.com/Vector35/binaryninja-api/pull/5461: Author: yrp <yrp604@protonmail.com> Date: Sat May 25 21:00:26 2024 -0700 arm64: lift sxtl, sxtl2, sshll, sshll2 Partial list of detailed changes squashed into this commit (see https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics for detailed commit history): * add lifting for sshll/sxtl * reverted neon_intrinsics.cpp to restore scvtf intrinsics * lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2 * reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases * added preferIntrinsics setting to arm64 * added lifting for movn * fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL * fix missing break in SCVT; optimize MOVK * improved preferIntrinsics * fixed bad lifting introduced for movn * fixed bad settings definition for preferIntrinsics * added intrinsic definition for DUP from general register * added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version * added direct lifting of scalar version of FABD, and fixed intrinsics for vector version * fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic * fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN * reviewed/fixed remaining intrinsics after SQXTUN * added lifting for FNMUL * WIP intrinsics improvements * WIP intrinsics improvements 2 * WIP intrinsics improvements: FCVT*_asisdmisc_R * added B.AL, B.NV, CASP* * direct lifting of scalar FSQRT instruction * SETREG now elides setting of targeting zero registers * fixed test_gen.py to correctly regenerate arm64test.py * unroll vector MOV operations, USHL no longer uses intrinsic for scalars * updated existing tests in arm64test.py for latest lifting changes * fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP) * lifting all variants of TBL as intrinsic * fixes/improvements to test_gen.py * lifting all variants of TBX as intrinsic * added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS * added tests for all aliases of SBFM | |||
| 2024-05-31 | improve efficiency | Zichuan Li | |
| 2024-05-31 | Fixed type propagation issue in AARCH64 and MIPS | Zichuan Li | |
| Previously, prtinf type library is not being appropriately applied. #3092 | |||
| 2024-03-15 | Separate local variable tokens in higher level ILs from stack variable ↵ | Rusty Wagner | |
| tokens in lower levels, and improve token usage in disassembly | |||
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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