| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-12-20 | Fix many of the warnings that show up when compiling with GCC 15.2 | Mark Rowe | |
| 2025-10-15 | [AArch64] Update disassembler based on 2025-09 ARM ISA data | Mark Rowe | |
| 2025-09-25 | [AArch64] Update disassembler based on 2025-06 ARM ISA data | Mark Rowe | |
| Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. | |||
| 2025-06-02 | ARM64 disassembler: fix MSVC compilation | justanotheranonymoususer | |
| 2025-05-28 | Revert "Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c" | Galen Williamson | |
| This reverts commit cb7c2d3bb716a2e96cf7f127bbf71992a4861907. | |||
| 2025-05-27 | Update decode_scratchpad.c | justanotheranonymoususer | |
| 2025-05-27 | Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c | justanotheranonymoususer | |
| MSVC shows several warnings, but this one is shown as an error, preventing compilation. | |||
| 2025-03-31 | [aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵ | Galen Williamson | |
| lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands | |||
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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