| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-04-22 | [arm64] Update header names in Makefiles | fG! | |
| The names of generated headers were not updated after they were changed in b095215397ca. | |||
| 2026-02-09 | Fix outdated object names in AArch64 disassembler Makefiles | Jon Palmisciano | |
| 2025-12-20 | Fix many of the warnings that show up when compiling with GCC 15.2 | Mark Rowe | |
| 2025-12-08 | [AArch64] Update system registers based on ARM's 2025-09 data | Mark Rowe | |
| This change consists of two parts: 1. Updating the system register enumeration and names based on the latest data from ARM. 2. Removing register names that conflict with the official names from ARM. The conflicting register names came a data set of Apple-specific system register names. These would ideally not be baked into the AArch64 disassembler at all, but would be added by Binary Ninja's Apple platform. The exact mechanism for doing that is still TBD. Fixes https://github.com/Vector35/binaryninja-api/issues/7664. | |||
| 2025-10-15 | [AArch64] Update disassembler based on 2025-09 ARM ISA data | Mark Rowe | |
| 2025-09-25 | [AArch64] Update disassembler based on 2025-06 ARM ISA data | Mark Rowe | |
| Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. | |||
| 2025-06-02 | ARM64 disassembler: fix MSVC compilation | justanotheranonymoususer | |
| 2025-05-28 | PR #6757: prefer fp, lr for x29, x30 | yrp | |
| arm64: prefer fp, lr arm64: update tests to use new reg names, improve windows build | |||
| 2025-05-28 | Revert "Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c" | Galen Williamson | |
| This reverts commit cb7c2d3bb716a2e96cf7f127bbf71992a4861907. | |||
| 2025-05-27 | Update decode_scratchpad.c | justanotheranonymoususer | |
| 2025-05-27 | Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c | justanotheranonymoususer | |
| MSVC shows several warnings, but this one is shown as an error, preventing compilation. | |||
| 2025-04-08 | [aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵ | Galen Williamson | |
| ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi | |||
| 2025-04-01 | [aarch64] use static var to avoid recreation of sysregs vector | Galen Williamson | |
| 2025-03-31 | [aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵ | Galen Williamson | |
| lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands | |||
| 2024-09-14 | Add mpidr_el1 aarch64 sysreg | Josh Ferrell | |
| 2024-09-13 | Fix many warnings | Josh Ferrell | |
| 2024-07-08 | [arm64] Full review of intrinsics; lifting of many instructions added, ↵ | Galen Williamson | |
| improved, and/or fixed Merged https://github.com/Vector35/binaryninja-api/pull/5461: Author: yrp <yrp604@protonmail.com> Date: Sat May 25 21:00:26 2024 -0700 arm64: lift sxtl, sxtl2, sshll, sshll2 Partial list of detailed changes squashed into this commit (see https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics for detailed commit history): * add lifting for sshll/sxtl * reverted neon_intrinsics.cpp to restore scvtf intrinsics * lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2 * reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases * added preferIntrinsics setting to arm64 * added lifting for movn * fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL * fix missing break in SCVT; optimize MOVK * improved preferIntrinsics * fixed bad lifting introduced for movn * fixed bad settings definition for preferIntrinsics * added intrinsic definition for DUP from general register * added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version * added direct lifting of scalar version of FABD, and fixed intrinsics for vector version * fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic * fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN * reviewed/fixed remaining intrinsics after SQXTUN * added lifting for FNMUL * WIP intrinsics improvements * WIP intrinsics improvements 2 * WIP intrinsics improvements: FCVT*_asisdmisc_R * added B.AL, B.NV, CASP* * direct lifting of scalar FSQRT instruction * SETREG now elides setting of targeting zero registers * fixed test_gen.py to correctly regenerate arm64test.py * unroll vector MOV operations, USHL no longer uses intrinsic for scalars * updated existing tests in arm64test.py for latest lifting changes * fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP) * lifting all variants of TBL as intrinsic * fixes/improvements to test_gen.py * lifting all variants of TBX as intrinsic * added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS * added tests for all aliases of SBFM | |||
| 2024-06-11 | Add some missing arm64 system registers | Josh Ferrell | |
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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