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path: root/arch/arm64/il.cpp
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2026-06-05[aarch64] Emit abs, min, and max instructions during liftingMark Rowe
2026-06-05[aarch64] Fix incorrect lifting of double precision FMOV immediateMark Rowe
2026-06-04[aarch64] Emit bswap, popcnt, clz, ctz, cls, and rbit instructions during ↵Mark Rowe
lifting Intrinsics are still used when lfiting vector instructions, and for 64-bit `rev16` instructions that are not easily composed from the new instructions.
2025-12-20Fix many of the warnings that show up when compiling with GCC 15.2Mark Rowe
2025-11-05[ARM64] only extend if load is smallyrp
[ARM64] remove zero extend from ubfx, ubfiz [ARM64] only zero extend fmov when needed arm64: resolve ambiguity Resolves #7307
2025-10-24aarch64: implements lifting (intrinsics) for LDXP/STXPMaxime Meignan
2025-10-20[AArch64] Lift MTE instructions to intrinsicsMark Rowe
2025-10-18[AArch64] Lift FEAT_CSSC instructionsMark Rowe
`abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction sequences involving comparisons, while `cnt` and `ctz` are lifted to intrinsics.
2025-09-25[AArch64] Update disassembler based on 2025-06 ARM ISA dataMark Rowe
Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions.
2025-09-18fix ldrsw lift to sign extend in certain encodingsyrp
2025-08-05[ARM64] Fix lifting of mrs xzr, ... to not reference the xzr registerMark Rowe
ARM64 lifting replaces references to the zero register with constant zeroes. The zero register is not intended to appear in any lifted IL. In the case of the `mrs` instruction, the destination being a zero register means the system register is accessed only for a side-effect, and is not stored anywhere. The lifting is updated to specify no output registers for the intrinsic in that case.
2025-07-30[ARM64] Fix lifting of tbz / tbnz for bits >= 32Mark Rowe
2025-04-09[aarch64] add lifting for B.NV instruction, fix branch generation for B.AL ↵Galen Williamson
and B.NV, fix AlwaysBranch patching to generate a valid B instruction
2025-04-09[aarch64] add lifting for B.AL instructionGalen Williamson
2025-04-08[aarch64] remove "unknown hint" warningGalen Williamson
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵Galen Williamson
ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
2025-03-31[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵Galen Williamson
lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands
2025-02-12bugfix: ARM64: missing break in il.cpp's switchMaxime Meignan
A `break` was missing in the switch, making the LDXRH instruction generate 2 IL instructions
2024-07-08[arm64] Full review of intrinsics; lifting of many instructions added, ↵Galen Williamson
improved, and/or fixed Merged https://github.com/Vector35/binaryninja-api/pull/5461: Author: yrp <yrp604@protonmail.com> Date: Sat May 25 21:00:26 2024 -0700 arm64: lift sxtl, sxtl2, sshll, sshll2 Partial list of detailed changes squashed into this commit (see https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics for detailed commit history): * add lifting for sshll/sxtl * reverted neon_intrinsics.cpp to restore scvtf intrinsics * lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2 * reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases * added preferIntrinsics setting to arm64 * added lifting for movn * fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL * fix missing break in SCVT; optimize MOVK * improved preferIntrinsics * fixed bad lifting introduced for movn * fixed bad settings definition for preferIntrinsics * added intrinsic definition for DUP from general register * added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version * added direct lifting of scalar version of FABD, and fixed intrinsics for vector version * fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic * fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN * reviewed/fixed remaining intrinsics after SQXTUN * added lifting for FNMUL * WIP intrinsics improvements * WIP intrinsics improvements 2 * WIP intrinsics improvements: FCVT*_asisdmisc_R * added B.AL, B.NV, CASP* * direct lifting of scalar FSQRT instruction * SETREG now elides setting of targeting zero registers * fixed test_gen.py to correctly regenerate arm64test.py * unroll vector MOV operations, USHL no longer uses intrinsic for scalars * updated existing tests in arm64test.py for latest lifting changes * fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP) * lifting all variants of TBL as intrinsic * fixes/improvements to test_gen.py * lifting all variants of TBX as intrinsic * added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS * added tests for all aliases of SBFM
2024-06-13[arm64]: fix broken compilation on windowsGalen Williamson
no Elvis operator ?:( api\arch\arm64\il.cpp(894): error C2059: syntax error: ':' api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20'
2024-06-13[arm64] fixed lifting for LDADD*, filled in lifting for alias STADD*, fixed ↵Galen Williamson
tests for recently added system registers dczid_el0 and ctr_el0; fixes #5603
2024-06-11Fix lifting of pair load operations when first and third operand are equal ↵Josh Ferrell
and reduce code duplication
2024-05-30[arm64] lift scvtfGalen Williamson
* only scalar variants for integer and floating point * updated arm64test.py for scvtf * removed intrinsics for scvtf, scalar integer and floating point variants
2024-05-29improve lifting of arm64 CSET instruction per Vector35/binaryninja-api#5134Galen Williamson
2024-03-05Move architecture modules into the API repoRusty Wagner