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Ran into this when running over certain object files on ppc, we can do it for all of them though.
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This change consists of two parts:
1. Updating the system register enumeration and names based on the
latest data from ARM.
2. Removing register names that conflict with the official names from
ARM.
The conflicting register names came a data set of Apple-specific system
register names. These would ideally not be baked into the AArch64
disassembler at all, but would be added by Binary Ninja's Apple
platform. The exact mechanism for doing that is still TBD.
Fixes https://github.com/Vector35/binaryninja-api/issues/7664.
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[ARM64] remove zero extend from ubfx, ubfiz
[ARM64] only zero extend fmov when needed
arm64: resolve ambiguity
Resolves #7307
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`abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction
sequences involving comparisons, while `cnt` and `ctz` are lifted to
intrinsics.
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Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
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ARM64 lifting replaces references to the zero register with constant
zeroes. The zero register is not intended to appear in any lifted IL.
In the case of the `mrs` instruction, the destination being a zero
register means the system register is accessed only for a side-effect,
and is not stored anywhere. The lifting is updated to specify no output
registers for the intrinsic in that case.
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This ensures that CMake detects when files that match the glob are added
or removed.
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Also update minimum CMake version.
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cause bugs and also issues with C++20
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arm64: prefer fp, lr
arm64: update tests to use new reg names, improve windows build
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This reverts commit cb7c2d3bb716a2e96cf7f127bbf71992a4861907.
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MSVC shows several warnings, but this one is shown as an error, preventing compilation.
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and B.NV, fix AlwaysBranch patching to generate a valid B instruction
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ST/LDSET, and their variants
Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
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lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture
* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands
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A `break` was missing in the switch, making the LDXRH instruction generate 2 IL instructions
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case from neon_intrinsics.cpp
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improved, and/or fixed
Merged https://github.com/Vector35/binaryninja-api/pull/5461:
Author: yrp <yrp604@protonmail.com>
Date: Sat May 25 21:00:26 2024 -0700
arm64: lift sxtl, sxtl2, sshll, sshll2
Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):
* add lifting for sshll/sxtl
* reverted neon_intrinsics.cpp to restore scvtf intrinsics
* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2
* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2
fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases
* added preferIntrinsics setting to arm64
* added lifting for movn
* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL
* fix missing break in SCVT; optimize MOVK
* improved preferIntrinsics
* fixed bad lifting introduced for movn
* fixed bad settings definition for preferIntrinsics
* added intrinsic definition for DUP from general register
* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version
* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version
* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic
* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN
* reviewed/fixed remaining intrinsics after SQXTUN
* added lifting for FNMUL
* WIP intrinsics improvements
* WIP intrinsics improvements 2
* WIP intrinsics improvements: FCVT*_asisdmisc_R
* added B.AL, B.NV, CASP*
* direct lifting of scalar FSQRT instruction
* SETREG now elides setting of targeting zero registers
* fixed test_gen.py to correctly regenerate arm64test.py
* unroll vector MOV operations, USHL no longer uses intrinsic for scalars
* updated existing tests in arm64test.py for latest lifting changes
* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)
* lifting all variants of TBL as intrinsic
* fixes/improvements to test_gen.py
* lifting all variants of TBX as intrinsic
* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS
* added tests for all aliases of SBFM
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no Elvis operator ?:(
api\arch\arm64\il.cpp(894): error C2059: syntax error: ':'
api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20'
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tests for recently added system registers dczid_el0 and ctr_el0; fixes #5603
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and reduce code duplication
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