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For 64-bit architectures, the results weren't properly sign-extended when
they were supposed to be for 32-bit operations.
This doesn't change the fact that the source of the register size is
still suspect, and this new sign extension may not properly take place for
64-bit architectures using 32-bit addresses, but solving that will take a
bit more examination in general.
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Except for SYNCI, I didn't have any test cases for these, but they're
fairly simple.
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This makes it easier to see which instructions still need to be lifted
versus those which never should be lifted.
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These aren't really needed; if it's for a 32-bit architecture that can't
handle 64-bit shifts, then the instruction won't be decoded in the first
place. Because the registerSize is derived from the address size, it may
interfere with 64-bit architectures that are using signed 32-bit
addresses.
There are a few other places that check registerSize (for example, the
32->64 bit sign extension idiom and MADD, MADDU) that are suspect, but
not included in this commit. The difference is that for 64-bit shifts,
checking at all for the register size is the problem; for those, the
check is still needed to figure out whether to sign extend or not, but
the value of registerSize is suspect.
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https://github.com/Vector35/binaryninja-api/issues/4028
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A user reported in public slack that the definition doesn't agree on
endianness
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case from neon_intrinsics.cpp
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improved, and/or fixed
Merged https://github.com/Vector35/binaryninja-api/pull/5461:
Author: yrp <yrp604@protonmail.com>
Date: Sat May 25 21:00:26 2024 -0700
arm64: lift sxtl, sxtl2, sshll, sshll2
Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):
* add lifting for sshll/sxtl
* reverted neon_intrinsics.cpp to restore scvtf intrinsics
* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2
* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2
fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases
* added preferIntrinsics setting to arm64
* added lifting for movn
* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL
* fix missing break in SCVT; optimize MOVK
* improved preferIntrinsics
* fixed bad lifting introduced for movn
* fixed bad settings definition for preferIntrinsics
* added intrinsic definition for DUP from general register
* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version
* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version
* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic
* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN
* reviewed/fixed remaining intrinsics after SQXTUN
* added lifting for FNMUL
* WIP intrinsics improvements
* WIP intrinsics improvements 2
* WIP intrinsics improvements: FCVT*_asisdmisc_R
* added B.AL, B.NV, CASP*
* direct lifting of scalar FSQRT instruction
* SETREG now elides setting of targeting zero registers
* fixed test_gen.py to correctly regenerate arm64test.py
* unroll vector MOV operations, USHL no longer uses intrinsic for scalars
* updated existing tests in arm64test.py for latest lifting changes
* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)
* lifting all variants of TBL as intrinsic
* fixes/improvements to test_gen.py
* lifting all variants of TBX as intrinsic
* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS
* added tests for all aliases of SBFM
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no Elvis operator ?:(
api\arch\arm64\il.cpp(894): error C2059: syntax error: ':'
api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20'
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tests for recently added system registers dczid_el0 and ctr_el0; fixes #5603
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and reduce code duplication
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Previously, prtinf type library is not being appropriately applied.
#3092
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* only scalar variants for integer and floating point
* updated arm64test.py for scvtf
* removed intrinsics for scvtf, scalar integer and floating point variants
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tokens in lower levels, and improve token usage in disassembly
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Make the CSR instructions show the CSR 12-bit immediate
operand as an unsigned integer.
This is a special case of the I-instruction format, where
it is same except that the 12-bit immediate is treated as
unsigned rather than signed.
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Signed-off-by: Visual Ehrmanntraut <30368284+VisualEhrmanntraut@users.noreply.github.com>
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Change integer register involved via compressed JAL
instruction from 0 (x0 (zero)) to 1 (x1 (ra))
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