| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-11-03 | Fix VLE ANDIx translation to always store result in destination register | chedahub | |
| 2025-11-01 | Fix PPCVLE I16L-form immediate decoding: use 5-bit mask for ui0_4 | chedahub | |
| 2025-10-29 | Fix(ppc/il): Treat r0 as a register in e_addi/e_add16i IL | chedahub | |
| 2025-10-29 | Fix(ppc/spe): Correct source operand parsing for EVX instructions | chedahub | |
| 2025-10-24 | aarch64: implements lifting (intrinsics) for LDXP/STXP | Maxime Meignan | |
| 2025-10-22 | Fix: PowerPC decode logic for Rx, Ry, Rz register | chedahub | |
| 2025-10-22 | Call SetIgnore on all intrinsic types in x86 | Peter LaFosse | |
| 2025-10-20 | [AArch64] Lift MTE instructions to intrinsics | Mark Rowe | |
| 2025-10-18 | [AArch64] Lift FEAT_CSSC instructions | Mark Rowe | |
| `abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction sequences involving comparisons, while `cnt` and `ctz` are lifted to intrinsics. | |||
| 2025-10-15 | [AArch64] Update disassembler based on 2025-09 ARM ISA data | Mark Rowe | |
| 2025-10-03 | Disable mpx mode in x86 as its been discontinued since 2019 | Peter LaFosse | |
| 2025-09-25 | [AArch64] Update disassembler based on 2025-06 ARM ISA data | Mark Rowe | |
| Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. | |||
| 2025-09-22 | [armv7] Add support for R_ARM_PC24 relocation | Nick Shipp | |
| 2025-09-18 | fix ldrsw lift to sign extend in certain encodings | yrp | |
| 2025-09-11 | Add Apple arm64 syscall calling convention to Apple's platforms | mostobriv | |
| 2025-09-08 | [aarch64] Enable Always and Never Branch patching for TBZ/TBNZ and CBZ/CBNZ | Galen Williamson | |
| 2025-08-20 | [Rust] Misc formatting fixes | Mason Reed | |
| 2025-08-14 | [Mac] Consistently specify rpaths for plug-ins | Mark Rowe | |
| C++ plug-ins now consistently use the `plugin_rpath` or `ui_plugin_rpath` macros to ensure they have `SKIP_BUILD_RPATH` set when building on Mac (i.e., no `LC_RPATH` is added). Rust plug-ins have their build.rs updated to only specify `-Wl,-rpath` when building for Linux. It is not needed on macOS. On macOS we instead explicitly specify an `@rpath`-relative install name. This doesn't change any behavior, but avoids leaving an absolute path as the library's install name and is consistent with CMake's behavior for C++ plug-ins. | |||
| 2025-08-14 | [thumb2] silence parentheses-equality warnings when compiling generated ↵ | Galen Williamson | |
| thumb2 disassembler | |||
| 2025-08-14 | [armv7] add explicit signedness to conversions for scalar forms of VCVT | Galen Williamson | |
| 2025-08-14 | [thumb2] improved disassembly and lifting of VCVT instruction for scalar ↵ | Galen Williamson | |
| floating-point/integer cases | |||
| 2025-08-14 | Corrected python docstring for LowLevelILFunction.float_convert | Galen Williamson | |
| [thumb2] removed redundant format suffixes from disassembly of VFP instruction [thumb2] Corrected lifting of VCVT instruction | |||
| 2025-08-14 | [armv7] Add lifting for VCVT floating-point scalar variants | Galen Williamson | |
| 2025-08-14 | [thumb2] Updated thumb2 disassembler generator to use Tatsu-generated parser ↵ | Galen Williamson | |
| instead of deprecated Grako | |||
| 2025-08-14 | [armv7/thumb2] Fix Lifting for PC-relative vldr instruction does not align ↵ | Galen Williamson | |
| PC when calculating address #6947 Updated thumb2 pcode parser used by disassembler generator to use Tatsu instead of deprecated Grako | |||
| 2025-08-05 | [ARM64] Fix lifting of mrs xzr, ... to not reference the xzr register | Mark Rowe | |
| ARM64 lifting replaces references to the zero register with constant zeroes. The zero register is not intended to appear in any lifted IL. In the case of the `mrs` instruction, the destination being a zero register means the system register is accessed only for a side-effect, and is not stored anywhere. The lifting is updated to specify no output registers for the intrinsic in that case. | |||
| 2025-08-01 | Add LogForException APIs to pass stack trace information separate from the ↵ | Rusty Wagner | |
| message | |||
| 2025-07-30 | [CMake] Specify CONFIGURE_DEPENDS for all file(GLOB ..) | Mark Rowe | |
| This ensures that CMake detects when files that match the glob are added or removed. | |||
| 2025-07-30 | [ARM64] Fix lifting of tbz / tbnz for bits >= 32 | Mark Rowe | |
| 2025-07-28 | [PPC] Make assembler.cpp compile over 30 times faster | Mark Rowe | |
| Clang was taking around 30 seconds to compile assembler.cpp on my machine, with most of its time spent in code generation for the global initializer for `lookup`. Changing the map key from `std::string` to `std::string_view` drops compile time to under a second. This is because the compiler no longer has to code gen the allocation, initialization, and moves of 2,100 `std::string`s. `std::string_view` is effectively free to initialize in comparison. While I was here I made the map `static const`. It's not required for the build time improvement, but it is more correct and helped me check that no-one is mutating the map. | |||
| 2025-07-21 | Fix crash on R_MIPS_HI16 relocs caused by bad cast | Brandon Miller | |
| 2025-07-03 | Fix compilation with newer clang/gcc versions | Josh Ferrell | |
| 2025-07-03 | arm/thumb: signal that returns can switch arch | Ryan Snyder | |
| 2025-07-02 | Fix mips tests failing to build on arm64 linux | Mason Reed | |
| 2025-07-02 | Fix thumb2 lifting to prevent temp reg spillover for post dec stm instruction. | Brian Potchik | |
| 2025-07-02 | [mips] Merges PR https://github.com/Vector35/binaryninja-api/pull/6311: MIPS ↵ | kat | |
| r5900 (PS2 EE) support | |||
| 2025-07-02 | Fix misc warnings in PPC disassembler | Mason Reed | |
| 2025-06-30 | [powerpc] Adjust default decoding modes in disassembler.cpp to improve ↵ | Galen Williamson | |
| coverage of instruction table in assembler.cpp | |||
| 2025-06-30 | [x86] Fixes #6628: "sysret should be considered a terminator #6628" by ↵ | Galen Williamson | |
| lifting XED_ICLASS_SYSRET* instructions as returns to RCX | |||
| 2025-06-29 | [powerpc] Full merge of PowerPC disassembler PRs, including: | Galen Williamson | |
| * Remove dependency on capstone for PowerPC disassembly #6292 * Add support for PowerPC VLE instruction set #6740 * Add support for paired-single instructions #6821 * Various post-merge fixes and tweaks to disassembly and lifting * Removal of dependence on capstone for assembler's scoring mechanism (capstone currently disabled, but not removed from codebase yet) | |||
| 2025-06-25 | Fix cxx20 compiler warnings. | Alexander Taylor | |
| 2025-06-25 | Update CXX_STANDARD to 20. | Alexander Taylor | |
| Also update minimum CMake version. | |||
| 2025-06-25 | Remove implicit conversions from Confidence to underlying type, these can ↵ | Rusty Wagner | |
| cause bugs and also issues with C++20 | |||
| 2025-06-09 | [thumb2] Converted MSR system registers into enum | Galen Williamson | |
| 2025-06-09 | WIP improve thumb2 MSR lifting | Galen Williamson | |
| 2025-06-09 | [thumb2] add intrinsics for rbit and clz instructions | Galen Williamson | |
| 2025-06-02 | Add IL for thumb2 CP instructions | jonathanzetier | |
| 2025-06-02 | Update README.md | jonathanzetier | |
| It looks like the build instructions hadn't been updated after the arch plugins were moved back to binaryninja-api. | |||
| 2025-06-02 | ARM64 disassembler: fix MSVC compilation | justanotheranonymoususer | |
| 2025-05-28 | PR #6757: prefer fp, lr for x29, x30 | yrp | |
| arm64: prefer fp, lr arm64: update tests to use new reg names, improve windows build | |||
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index : public/binaryninja-api.git | |
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