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path: root/arch/mips/il.cpp
AgeCommit message (Collapse)Author
2025-12-20Fix many of the warnings that show up when compiling with GCC 15.2Mark Rowe
2025-12-11[MIPS] Mark `jalr[.hb] $zero, $ra` as a return instructionRong "Mantle" Bao
2025-07-02[mips] Merges PR https://github.com/Vector35/binaryninja-api/pull/6311: MIPS ↵kat
r5900 (PS2 EE) support
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵Galen Williamson
ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
2025-02-06[mips] Fix decoding of MIPS ds*32 instructions, add lifting for MIPS drotr* ↵Galen Williamson
instructions; clean up some warnings in powerpc/il.cpp
2024-08-12Add decode, disassembly, IL for TLBINV, TLBINVFnoone
2024-08-12Sign-extend results of 32-bit operations on HI, LOnoone
For 64-bit architectures, the results weren't properly sign-extended when they were supposed to be for 32-bit operations. This doesn't change the fact that the source of the register size is still suspect, and this new sign extension may not properly take place for 64-bit architectures using 32-bit addresses, but solving that will take a bit more examination in general.
2024-08-12Add IL, intrinsics for TLB-related instructionsnoone
2024-08-12Add intrinsics for some system instructionsnoone
Except for SYNCI, I didn't have any test cases for these, but they're fairly simple.
2024-08-12Differentiate some enums in IL switch statementnoone
This makes it easier to see which instructions still need to be lifted versus those which never should be lifted.
2024-08-12Remove checks for 64-bit shift instructionsnoone
These aren't really needed; if it's for a 32-bit architecture that can't handle 64-bit shifts, then the instruction won't be decoded in the first place. Because the registerSize is derived from the address size, it may interfere with 64-bit architectures that are using signed 32-bit addresses. There are a few other places that check registerSize (for example, the 32->64 bit sign extension idiom and MADD, MADDU) that are suspect, but not included in this commit. The difference is that for 64-bit shifts, checking at all for the register size is the problem; for those, the check is still needed to figure out whether to sign extend or not, but the value of registerSize is suspect.
2024-07-08Add Cavium Octeon MIPS Instructions and more general MIPS fixesnoone
2024-03-05Move architecture modules into the API repoRusty Wagner