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This appears to fix a bug in a TriCore unit test for reasons I don't
fully understand.
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All bundled under the arch_bintxt/arch_bintext view plugin
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Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV
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Also fix some formatting issues
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System registers needed to be marked to prevent the registers from being passed as arguments
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VSUB already existed but it was lifted as a regular SUB instruction
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Any usage of d15, s15, q15 was completely broken
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Found this while testing some MSP430 binaries with the new support being
added. I had the logic correct, but forgot to tell Rust that overflow
was expected.
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This patch has existed on the cpp sample plugin for a while, just finally merging it into api.
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