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path: root/arch/arm64/disassembler/sysregs_gen.h
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2025-12-08[AArch64] Update system registers based on ARM's 2025-09 dataMark Rowe
This change consists of two parts: 1. Updating the system register enumeration and names based on the latest data from ARM. 2. Removing register names that conflict with the official names from ARM. The conflicting register names came a data set of Apple-specific system register names. These would ideally not be baked into the AArch64 disassembler at all, but would be added by Binary Ninja's Apple platform. The exact mechanism for doing that is still TBD. Fixes https://github.com/Vector35/binaryninja-api/issues/7664.
2025-09-25[AArch64] Update disassembler based on 2025-06 ARM ISA dataMark Rowe
Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions.
2025-04-01[aarch64] use static var to avoid recreation of sysregs vectorGalen Williamson
2025-03-31[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵Galen Williamson
lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands